A PLL is an electronic circuit, which generates an output signal that has a well-controlled relationship in phase and frequency to an input signal. PLLs are used in numerous applications including, for example, I/O interfaces of digital integrated circuits, memory systems, processors, frequency multiplication or frequency tracking. A PLL may be included in a multi-data rate interface that transfers data at different data rates or a circuit that operates in different modes of operation, such as a typical transfer mode of operation and a debug/test mode of operation.
Accordingly, it is desirable to have a PLL that can operate at a selected frequency range for a particular mode of operation or operate at multiple discrete frequency ranges.
However, a PLL is typically designed to operate at the highest specified input frequency. A frequency range of a voltage-controlled oscillator (“VCO”), in the PLL, generally operates at about two times the minimum specified input frequency of the PLL. So, often a designer would implement VCOs with high frequency ranges in order to meet specified high frequency inputs; while increasing the minimum input operating frequency of the PLL. Although, by designing for high frequency input performance, PLL performance at lower input frequencies degrades.
A PLL may be modified to enable improved performance at lower input frequencies; however, the modified PLLs have certain disadvantages. First, a programmable divider may be added to the output signal of a PLL. Thus, a high frequency output signal is divided down to a selected lower frequency. However, the period of the lower frequency output signal is limited to integral multiples of the specified high frequency. Further, for applications that use a large number of clock buffers for the output signal, a programmable divider positioned after the clock buffers will cause the PLL using clock buffers to draw more power than would be necessary at lower frequencies.
Second, a modified PLL may include a VCO with switchable capacitance. However, maximum frequency of the VCO will be reduced by the addition of the load of the switch. Also, capacitance that increases circuit area would be required for a low frequency.
Third, a modified PLL may include a VCO with multiple taps similar to a divider circuit. However, this will create an uneven mixer output phase, and increase circuit complexity.
Fourth, two or more PLLs may be used. However, this will increase power consumption, circuit area, and circuit complexity.
Therefore, it is desirable to provide a PLL that can operate in a selected operating frequency range without the above-described disadvantages, to accommodate a PLL application that may communicate with different signal levels or with multiple discrete operating frequencies (i.e. multi-data rate, bi-modal, multi-modal integrated circuits).